Vikas Talwar
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nSys_v2vhd: nSys_v2vhd is a source code translator which translate Verilog RTL code into VHDL. The translator is written for a subset of the Verilog grammer, taken from IEEE specifications. nSys_v2vhd generates neat code and most of the time, the resulting code is compliable without any manual editing. |
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nSys_ncc:
nSys_v2vhd is a source code analyzer. It takes source code files and input and generate report on standard output.
Report includes: 1)
Total number of Lines. 2) Commented Lines. 3) Blank Lines. 4) Code Lines. 5) Number of Tasks/Functions within File. 6) Number of Lines within
Tasks/Functions. 7) Commented/Blank/Code Lines within Tasks/Functions. Additional Features: 1) Remove code from input
file. 2) Remove blank lines from input code. 3) Remove code from input file.
thanks for visiting
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Vikas Talwar
Projects Done
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Projects in nSys:
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nSys_v2vhd: nSys_v2vhd is a source code translator which translate Verilog RTL code into VHDL. The translator is written for a subset of the Verilog grammer, taken from IEEE specifications. nSys_v2vhd generates neat code and most of the time, the resulting code is compliable without any manual editing. |
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nSys_ncc:
nSys_v2vhd is a source code analyzer. It takes source code files and input and generate report on standard output.
Report includes: 1)
Total number of Lines. 2) Commented Lines. 3) Blank Lines. 4) Code Lines. 5) Number of Tasks/Functions within File. 6) Number of Lines within
Tasks/Functions. 7) Commented/Blank/Code Lines within Tasks/Functions. Additional Features: 1) Remove code from input
file. 2) Remove blank lines from input code. 3) Remove code from input file.
thanks for visiting
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