![]() |
![]() |
![]() |
![]() |
![]() |
|
![]() |
![]() |
![]() Vikas Talwar Resume |
![]() |
||
![]() |
![]() |
![]() |
![]() |
||
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
|||||
![]() |
![]() |
||||
![]() |
![]() |
||||
![]() |
![]() |
Rohini - 8,
Delhi, India
|
![]() |
![]() |
![]() |
||||
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
Objective:
To find a fulfilling career that makes the best use of my skills.
Experience:
Trainee Software Engineer (1/3/04-Till Date)
Working as trainee software engineer in nSys Design Systems Private Limited, New Delhi
Education:
MCA, Punjab Technical University, 2004
B.Com (H), Delhi University, 2001
.
Skills:
Languages: C/C++/Java
Scripting: Perl-CGI, Shell
Tools: Lex/Yacc
Projects in nSys:
nSys_v2vhd: VERILOG to VHDL Converter (for RTL code)
nSys_ncc: Source Code Analyzer (supports VERILOG/VHDL/VERA/SystemC)
codeGen: Source Code Generator for nVs (nSys Verification System)
Web: Designed web pages for nSys's Intranet.
.
.
|
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
![]() |
||||
![]() |
![]() |
References Available on Request thanks for visiting
|
![]() |
![]() |
![]() |
||||
![]() |
||||
![]() |
||||